Most digital circuits require undriven inputs to be biased to a valid high or low voltage level. Conventional bias circuitry typically utilizes a fixed pull-up or pull-down resistor or latch that biases an input to its last driven state.
In the case of a fixed bias circuit for a synchronous or clocked system having an intermittent undriven state, e.g., multiple bidirectional cells connected together as a bus, the bias circuit may repeatedly charge a net (an unbroken, conductive medium connecting active and passive devices into a single circuit) from its driven state to a biased state. When the driven and biased states are at opposite logic levels, the transition from the driven state to the biased state exhibits the exponential time response of a simple RC circuit. As the net charges, the current through and voltage across a bias resistor exponentially decreases toward zero. A bias circuit using passive bias resistors may require as many as three time constants to charge a net through the opposite logic threshold, e.g., from a low to a high voltage level.
Pull-up or pull-down biasing functions are often integrated into the input/output (I/O) cells (I/O drivers of an IC on which the bias circuit resides) of application specific integrated circuits (ASICs). However, on-chip resistors used in typical bias circuits have poor tolerances and require more silicon area than transistors. Although transistors can be switched "ON" and "OFF" and use much less silicon area, saturated transistors present an even worse tolerance problem over process, voltage, and temperature.
Therefore, conventional bias circuits present several disadvantages when applied to integrated circuit design. As previously discussed, the time required for a bias circuit to transition from one digital logic state to another is one of the impediments to meeting faster integrated circuit clock speed specifications. Additionally, conventional bias circuits use components which do not promote efficient use of valuable silicon wafer surface area. Further, due to the integrated circuit manufacturing process, the tolerances of conventional bias circuit components are not predictably consistent for close tolerance applications.